Historically, most printed circuit board (PCB) testing was done using in-circuit test equipment. Recent advances with VLSI technology now enable microprocessors and Application Specific Integrated Circuits (ASICs) to be packaged into fine pitch, high count packages. These high density devices pose unique manufacturing challenges, such as the accessibility of test points and the high cost of test equipment.
Boundary scan testing was developed as the JTAG (Joint Test Access Group) interface, and formalized as the IEEE 1149.1 standard, to solve the physical access problems on PCBs caused by increasingly crowded assemblies due to the dense packaging technologies. Boundary scan embeds test circuitry at the chip level to form a complete board-level test protocol. With boundary scan, even the most complex assemblies can be accessed for testing, debugging, in-system device programming, and for diagnosing hardware problems.
Boundary scan is a methodology allowing complete control and observation of the boundary pins of an IEEE 1149.1 compatible device via software control. The IEEE 1149.1 standard defines a four-wire serial interface used to access complex integrated circuits (ICs) such as microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), and Complex Programmable Logic Devices (CPLDs). An on-chip test bus circuitry that complies with the IEEE 1149.1 standard includes boundary scan registers and a test access port (TAP) controller to execute the boundary scan functions. The TAP controller is a finite-state machine that decodes the state of the bus.
The boundary scan bus circuitry consists of the boundary scan registers, a 1-bit bypass register, an instruction register, several miscellaneous registers, and the TAP controller. The boundary scan bus consists of a test clock signal (TCK) pin, a test mode signal (TMS) pin, a test data in (TDI) line, a test data out (TDO) line, and a test reset (TRST) pin.
The TCK pin and the TMS pin direct signals between the TAP controller states. The TDI pin and the TDO pin receive the data input and output signals, respectively, for the boundary scan register chain. Optionally, a fifth pin, TRST, can be implemented as an asynchronous reset signal to the TAP controller.
During standard operations, the boundary scan registers are inactive and allow data to be propagated through the boundary scan device normally. During test modes, all input signals are captured for analysis and all output signals are preset to test down-string devices. The operation of these boundary scan registers are controlled through the TAP Controller and an instruction register.
Test instructions and test data are sent to a chip over the TDI line. Test results and status information are sent from a chip over the TDO line. This information is transmitted serially. Control of the boundary scan bus circuitry is carried out by the TAP controller, which responds to the state transitions on the TMS line. The boundary scan logic is clocked by the TCK signal.
The boundary scan registers are configured as a chain. A first boundary scan register in the chain is driven by the TDI line, and the last boundary scan register drives the TDO line. The instruction register provides the specific instructions related to the type of test that is to be performed. The IEEE 1149.1 Standard requires that all compliant devices must perform the EXTEST instruction, the SAMPLE/PRELOAD instruction, and the BYPASS instruction. The EXTEST instruction performs a PCB interconnect test. The EXTEST instruction places an IEEE 1149.1 compliant device into an external boundary test mode and selects the boundary scan register to be connected between the TDI pin and the TDO pin. During this instruction, the boundary scan registers associated with the outputs are preloaded with test patterns to test downstream devices. The input boundary scan registers are set up to capture the input data for later analysis. The SAMPLE/PRELOAD instruction allows an IEEE 1149.1 compliant device to remain in its functional mode and selects the boundary scan register to be connected between the TDI pin and the TDO pin. During this instruction, the boundary scan register can be accessed via a data scan operation to take a sample of the functional data entering and leaving the device. This instruction is also used to preload test data into the boundary scan registers prior to loading an EXTEST instruction. A boundary scan register chain can be skipped using the BYPASS instruction, allowing the data to pass through the bypass register. The BYPASS instruction allows an IEEE 1149.1 compliant device to remain in a functional mode and selects the bypass register to be connected between the TDI pin and the TDO pin. The BYPASS instruction allows serial data to be transferred through a device from the TDI pin to the TDO pin without affecting the operation of the device.
Multiple scan-compatible ICs may be serially interconnected on the PCB, forming one or more boundary scan chains, each chain having its own TAP. Each scan chain provides electrical access from the serial TAP interface to every pin on every IC that is part of the chain. In normal operation, the IC performs its intended function as though the boundary scan circuits were not present. However, when the device's scan logic is activated for the purpose of testing or in-system programming, data can be sent to the IC and read from it using the serial interface. This data may be used to stimulate the device core, drive signals outward from the device pins to the PCB, sense the input pins from the PCB, and sense the device outputs.
The boundary scan registers are located close to the pad area of the chip under test. Due to physical constraints of the printed circuit board, a boundary scan device, and its boundary scan registers, can not always be located as close to the pin under test as is optimal. Further, the circuit path length from the pin under test to each boundary scan register varies in length, which results in delay. Other factors also contribute to incongruent delay, such as temperature. Further, the clock signal that triggers a particular boundary scan register is generated from the TAP controller, and distributed to the boundary scan registers. For ideal boundary scan register path design, any data delay from one boundary scan register to another should match the clock skew between registers, so that the boundary scan register does not receive the wrong data. However, in practice the order of data transmission does not track with the clock distribution path. To overcome this disparity, a delay can be inserted on the data path between two boundary scan registers. Accounting for such delays though, across all temperature and process variations, is difficult and burdensome. Moreover, for a high-capacity chip, which has many I/O and control pins, there are many different boundary scan register paths to consider.
FIG. 1 illustrates a conventional chain of two boundary scan registers configured according to ideal conditions. A boundary scan register FFn and a boundary scan register FFn+1 are configured in series such that an output from the boundary scan register FFn is provided as an input to the boundary scan register FFn+1. The conventional chain is configured such that a one-phase clock signal is provided as the clock input signal cktst to each of the boundary scan registers in the chain, including the boundary scan register FFn and the boundary scan register FFn+1. In the ideal case illustrated in FIG. 1, there is no clock signal delay between the clock signal received by the boundary scan register FFn and the boundary scan register Ffn+1. Accordingly, data racing does not occur. The ideal case also represents those occurrences where the clock skew between the two boundary scan registers FFn and FFn+1 is less than the value tKQ plus data line delay, where the value tKQ represents the time delay of the boundary scan register FFn to provide the data to the boundary scan register FFn+1.
FIG. 2 illustrates the waveforms associated with the boundary scan registers configured according to FIG. 1. The boundary scan register FFn latches the data 1a received at the input D of the register FFn. At the rising edge of the clock signal cktst, the data 1a latched by the boundary scan register FFn is provided at the output Q of the boundary scan register FFn, illustrated as Q(FFn) in FIG. 2. The boundary scan register FFn+1 latches the data Q(FFn) as data 2a. At the rising edge of the clock signal cktst, the data 2a latched by the boundary scan register FFn+1 is provided at the output Q of the boundary scan register FFn+1, illustrated as Q(FFn+1). The ideal boundary scan register chain shown in FIG. 1 successfully shifts data from cycle to cycle. However, under normal configurations and operating conditions, significant delays are introduced whereby data racing problems occur.
FIG. 3 illustrates a chain of two conventional boundary scan registers in which timing delays result in data racing. FIG. 4 illustrates the waveforms associated with the chain of boundary scan registers illustrated in FIG. 3. If the clock skew between the two boundary scan registers is larger than the delay tKQ of the boundary scan register FFn plus the data line delay, then the data 1a which should be latched by the boundary scan register FFn+1 at the second cycle, is instead latched at the first cycle. This results in a data timing race problem. If the clock signal cktstn+1 provided to the boundary scan register FFn+1 is delayed enough, then when the data is output from the boundary scan register FFn to the boundary scan register FFn+1, the data simply flows through the boundary scan register FFn+1 as long as the clock signal cktstn+1 is high. Racing problems occur because the clock distribution path is usually not tracking with the data transmitting path. This problem cannot be resolved even when the system cycle time TCK is relaxed. Data racing can be fixed by adding a delay on the data path. However, it is difficult to match the transistor delay to the metal wire RC delay in all process corners, power supply levels and temperatures. Matching these delays significantly increases the overhead.